This application claims priority from a Korean Application, entitled xe2x80x9cDual Level Substrate Voltage Generatorxe2x80x9d Application No. 2000-36959, Republic of Korea, and filed on Jun. 30, 2000 and incorporates by reference its disclosure for all purposes.
1. Field of the Invention
The present invention relates to a dual-level substrate voltage generator, and, more particularly, to a dual-level substrate voltage generator that stably controls a substrate voltage when a current is suddenly flowed (i.e., surges) into a substrate power supply in a negative wordline structure, or during the activation of a chip.
2. Description of the Prior Art
In general, a substrate bias voltage Vbb is applied to a P-well surrounding an NMOS transistor. Vbb is hereinafter referred to as a xe2x80x9csubstrate biasxe2x80x9d since the voltage Vbb is applied to a p-type silicon substrate typically used as a DRAM substrate. The Vbb voltage is provided by an internal substrate bias circuit (e.g., on-chip) that generates a voltage of approximately xe2x88x922V to 3V from a power supply with Vcc=5V.
Vbb voltage is applied to the power supply circuit to prohibit a loss or latch-up of data in a memory cell by preventing a PN junction within a memory chip from being forward-biased. That is, even if a voltage undershoot of xe2x88x922V is received in an input waveform of a signal fed to a data input terminal, the PN diode fails to turn on, thus preventing electrons from the input terminal from flowing into the p-type silicon substrate.
Applying substrate bias voltage Vbb to the power supply circuit also decreases the change in threshold voltage of the MOS transistor due to a back-gate effect or a body effect stabilizes the operation of the chip.
It is essential that a substrate bias voltage Vbb is applied to the memory cell region, because as transistors scale to higher densities, and an increase in the density of substrate and well concentrations per unit area produce an increase in fluctuation in threshold voltage to the substrate bias voltage Vbb (i.e., a bulk effect).
As mentioned above, substrate bias voltage Vbb functions as a power supply which prevents a loss or latch-up of data in the memory cell, and in turn increases the threshold voltage of the MOS transistor. This decreases fluctuations in the threshold voltage of the MOS transistor, thereby stabilizing the operation of the circuit.
Referring to the drawings, FIGS. 1 and 2, are respectively a schematic block diagram and an illustration of the generation and feedback process of substrate bias voltage Vbb in the prior art.
As shown in FIG. 1, substrate voltage generation block 1 is a driver for pumping a voltage to generate a substrate voltage Vbb. Substrate voltage detection block 2 senses a level of substrate voltage Vbb fed from substrate voltage generation block 1 and outputs a substrate voltage control signal which is used to initiate an output to substrate voltage generation block 1 for generating a specific level (i.e., targeted level) of Vbb. In hit operation, a power-up of a device renders the substrate voltage control signal to a logic high, allowing substrate voltage generation block 1 to generate Vbb. If the level of Vbb corresponds to the specific level, substrate voltage detection block 2 will detect the targeted level and outputs the substrate voltage control signal as a logic low, stopping the pumping operation of substrate voltage generation block 1.
When the Vbb level is increased during operation in either an active mode, a pre-charge mode, or any other current consuming mode, substrate voltage detection block 2 outputs the substrate voltage control signal to voltage generation block 1 with a logic high value. As a result, substrate voltage generation block 1 is enabled to compensate for the increased Vbb level.
FIG. 2 shows a waveform chart of the Vbb level during, for example, an active or pre-charge mode. When the Vbb level is logic high or logic low, the Vbb level has sharp fluctuations. However, when a considerable current is suddenly dissipated during the operation of the chip, i.e., in active or pre-charge mode, the conventional substrate voltage generator performs a pumping operation to control the Vbb level, thereby compensating for the sudden change in current. Accordingly, a conventional circuit suffers from drawbacks in that it results in delayed response time and overpumping, and causes a sudden fluctuation in voltage level, which makes it difficult to control the substrate voltage level, thus adversely affecting the overall operation of a chip.
The present invention provides a dual-level substrate voltage generator capable of maintaining a level of the substrate voltage quickly and stably by generating a second substrate voltage having a level lower than that of a first substrate voltage and dividing the charge, to thereby reduce sudden current dissipation during an active or precharge mode.
In accordance with a preferred embodiment of the present invention, there is provided a dual-level substrate voltage generator comprising a first voltage generating means for generating a first substrate voltage; a first voltage detecting means for detecting the level of the first substrate voltage fed from the first voltage generating means, the detecting means outputting a first substrate voltage control signal, which is used to initiate output of the first substrate voltage at an optimum level, a second voltage generating means for generating a second substrate voltage with a level lower than that of the first substrate voltage, a second voltage detecting means for detecting the level of the second substrate voltage fed from the second voltage generating means, the second detecting means outputting a second substrate voltage control signal, which initiates the output of the second substrate voltage to the second voltage generating means at an optimum level, and a switching means for performing a switching operation during a current consuming mode, such as an active or pre-charge mode. The switching means functions to divide the charge on between the first and second substrate voltages, such that charge is shared or exchanged to compensate for fluctuations in the first substrate voltage.